1. 3 months’ probation period for candidates with experience, or,
2. 6 months’ probation period for fresh graduate candidate without experience

• BSEE/BSCE (Masters preferred) & outstanding hands-on FPGA design and development experience on either Altera or Xilinx
• Expert experience with Verilog (or possibly VHDL) RTL design and high-speed digital design methodologies.
• FPGA Code development/design experience with either Xilinx or Altera
• FPGA Verification & Debug experience using ModelSim, (Perl, Python).
• Experience in floor planning, synthesis, and placement & routing; Xilinx and Altera is ideal
• Experience with writing BFM, monitors (PCI/PCIe, USB, and DDR2/3), and test benches.
• Extensive packet processing experience as well as full-chip verification
• Outstanding communication skills and strong problem-solving abilities.
• Knowledge and skill in Programming Languages as per following:
  • Field Programmable Gate Arrays (FPGAs)
  • VHSIC Hardware Description Language (VHDL)
  • VeriLog
• Willing to work on-site (in Bukit Jalil, Kuala Lumpur)

• Design and Verification of FPGAs with Verilog/VHDL
• Optimizing FPGA code to minimize resources / maximize clock speed.
• Verification of FPGAs using ModelSim, etc.
• Debug FPGA issues on the hardware platform
• Invent, document, and implement micro-architecture and design details for new-product features.
• Physical implementation in FPGA targets for emulation; timing closure, debug

** Please note that we didn’t post for Fresh Graduate as we intended to find it through University